Q3a: FSM

https://hdlbits.01xz.net/wiki/Exams/2014_q3fsm

module top_module (

    input clk,

    input reset,   // Synchronous reset

    input s,

    input w,

    output z

);

    localparam 

        A    = 3'd0,

        B   =  3'd1, 

        C   =  3'd2,

        D   =  3'd3,

        E   =  3'd4;

    reg [2:0] state, next_state;

    reg [2:0] W_VA;

    

   always @ (*)

        case (state)

            A: next_state = s?B:A;

            B: next_state = C;

            C: next_state = D;

            D: next_state = E;

            E: next_state = C;

            default next_state = A;

        endcase

    always @ (posedge clk)

        if (reset)

            state <= A;

        else

            state <= next_state;

    always @ (posedge clk)

        case (next_state)

            C:W_VA <= {2'b00,w} ;

            D:W_VA <= {W_VA[2],w,W_VA[0]};

            E:W_VA <= {w,W_VA[1:0]};

            default W_VA <= 3'b000;

        endcase

    assign z =  next_state == C && ((W_VA==3'b011)  || (W_VA==3'b101) || (W_VA==3'b110));     

endmodule