在芯片工艺提升的道路上，人类做了哪些创新？

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半导体芯片，人类文明史上最耀眼的智慧结晶之一

Semiconductor chip, one of the most dazzling wisdom crystals of all the time

其设计与制造之精巧，让人类自己都惊叹不已

Even human are amazed of its designing and making compactness

但它说到底也要从最基础的结构——晶体管出发

But it’s based on the basic structure, transistor

你好

Hello

这里是一个成功忘拿了麦克风不得不拿手机录音的屑up

This is an unlucky up who succeeded to forget to get his microphone

今天我们看一看，在芯片工艺提升的道路上，人类做了哪些创新

Today, let’s talk about what creations made by human in chip craft development

 

 

芯片工艺的提升，主要就是晶体管工艺制程的压缩

Chip craft’s improvement mainly depends on compressing to transistor craft process

还记得中学物理课本上的这张图吗

Did you still remember this picture in middle school physical textbook?

在铁片上施加电压，按照电阻定律R=ρL/S

Apply voltage to the iron sheet, according to R=ρL/S

只要同步裁剪长度和横截面积就能做到电阻不变，相等电压下电流也不变

Current equals the past in the same voltage as long as you change its length and Cross-sectional area synchronously

只是散热面积减小

Merely the heat dissipation area decreases

所以在集成电路发展的早期，人们主要面对的是功耗而非玄学问题

So in early time of IC development, the main problem is power consumption, not metaphysical

但现在我们确实在面临玄学问题

But we need to face it now

究竟怎么个玄法，就要从半导体本身出发

Let’s discuss it from semiconductor itself

 

单晶硅和金刚石的结构一样都是对称的四根共价键连着

Signal crystal Si has the same structure as diamond, with 4 symmetrical sharing bonds

在这样的本征半导体中掺杂第三主族元素（例如B）会缺少一个电子形成空穴，曰P型半导体

Doped the 3rd main group element(eg : B) in intrinsic semiconductors, and you will lose a electron and get a cavity. This is P-type semiconductor.

掺杂第五主族元素（例如P）会有多余的自由电子，曰N型半导体

Doped 5th main group element(eg : P) and you will get another free electron. This is N-type semiconductor

二者挨着时空穴与自由电子之间会形成一个内部电场

When P and N type next to each other, cavities and free electrons will make an internal electric field

当外界施加正向电压时内部电场推着电子走，反向电压时挡着电子走，电阻不一样

When you apply forward volt it will push electrons and stop when the reverse volt, so it has different resistances

这就是二极管内PN结的单向导电性

Which is called unidirectional conductivity of the PN junction inside the diode

而三极管有发射极、集电极和基极三个电极

The 3-electrode-transistor has emitter, collector and base

以NPN的为例，当与P区相连的基极吸收少量来自发射极的自由电子时

For an example as NPN type, when the base next to P field absorbs few free electrons from the emitter

集电极会吸收大部分，从而放大输入的电流或电压信号，甚至实现控制开关的作用

The collector will absorb the most, so that it can zoom inputting current or volt signals, even become a switch

但后来科学家们发明了金属氧化物半导体场效应管（MOSFET）

But scientists invented MOSFET

它有源极、漏极、栅极和衬底四部分

It has Source, drain, gate, and substrate

还是以NPN的为例，源极和漏极都连着N型半导体，内含大量自由电子

For NPN type, the source and drain connect to N-type semiconductor with many free electron

而栅极在两方之间，用二氧化硅隔开

The gate is between them and is separated by SiO2

当我们在栅极与衬底之间施加一定的正向电压时

When we apply volt from the gate to the substrate

会有大量电子被吸过来在源极和漏极形成N沟道，从而导电

Many electrons will be absorbed there to form a N-channel and conductive

通过对栅极电势的修改实现压控电阻和控制开关

You can implement a volt-control resistance or a switch

由于二氧化硅绝缘使得MOSFET的输入电流与功率为0，降低了功耗，从而压缩了芯片的工艺制程

Insulating SiO2 leads inputting current and power to 0, reduces power consumption, and compresses the process

但是这有个前提是栅极不向漏极漏电

However, you need to be sure that the gate won’t creepage to the drain

很不幸，现在有个玄学问题摆在你面前——量子遂穿

Unluckily, now there is a metaphysical problem. quantum penetration

 

按照德布罗意的物质波观点，电子也有波粒二象性

According to De Broglie’s matter wave view, electron also has wave-particle duality

电子的轨道就是驻波存在的结果

Orbits are a result of standing waves

于是科学家们提出波函数的概念

So scientists point out wave function

它表示某处某时出现概率（或概率密度）的相对大小，正比于波的能量

It represents the relative magnitude of the probability (or probability density) of occurrence at a certain time, proportional to the energy of the wave

一个地方的波函数值越大，粒子在这里出现的可能性也就越大

The large wave function value in a place, the more possible a particle appears there

以一维坐标系为例，设电子的动量与约化普朗克常数之比为k

In 1D coordinate system, let k=p/hbar

结合能量量子化 以及动量与动能的关系

As you know  and

可得             than you find

代入波动方程~后得波函数ψ=~

Put them into wave equation and get the wave function psi=~

接着对x和t分别求二阶和一阶导数，获取动量与能量算子

Then find the second and first derivatives for x and t, respectively, to obtain the momentum and energy operators

设电子一开始具备E的动能且势能为0

Let an electron has moving energy E and potential energy 0

现在，在电子前面有一个势垒，爬上去就会有U的势能

In front of it exists a barrier with potential energy U

你会理所当然地认为只E>U时电子才有足够的能量越过去

You must say, the electron will fly over it only when E>U

这就和撑杆跳时要积攒弹性势能才能跳过去没有什么区别

just like accumulating elastic potential energy to jump through a pole vault

但实际上，当E<U时，k和p的值依然存在，只不过是虚数

Instead, when E<U, k and p are still exist, although they are image numbers

此时经过一系列数学变换，有~

At this time, after a series of mathematical transformations, there is ~

波函数的二阶可导意味着它一定是自身和一阶连续的

Wave function is 2nd derivable means it and its 1st derivative are continuous

利用势垒的边界条件得出，当取势垒左边的x时波函数大于0

Use barrier’s boundary condition to find that ψ>0 when x is left

这很好理解，是电子被势垒反弹回来了

It’s easy to understand because the electron is bounced back by the barrier

但是取势垒右边的x时波函数依旧大于0，也就是说，电子有一定的概率出现在右边

But ψ>0 even x is right, other words, electrons have some possibility to appear in the right

这就是量子遂穿，也叫势垒贯穿

That’s quantum penetration, also called barrier penetration

 

为了让栅极和漏极之间电流足够小，有较强的控制力

To reduce the current between the gate and the drain so as to get strong control

栅极和沟道之间必须有足够大的接触面积

The gate must have large enough exposure area with the channel

传统的工艺只是让栅极和氧化层平铺在上面

Traditional process paves gates and dioxide on chips

但随着晶体管越来越小，栅极宽度已经小到无法让平铺的工艺解决漏电难题

But with the shrinking of transistors, gate width is to small to face this problem

所以22nm以后，人们将过去挖坑式的源极和漏极立了起来

So after 22nm, someone The source erects gates and drains of the previous digging type

栅极和氧化层绕着源极和漏极，形成一个鱼鳍式的结构

The source and drain are surrounded by the gate and dioxide and form a structure like fin

三面环绕使得接触面积大大增加，这就是鳍式晶体管（FinFET）

3 sides surrounding enlarges the exposure area, that is FinFET

那既然三面环绕，可不可以再彻底一点，四面环绕呢？

So, why not change 3 sides to 4 sides?

这时，我们需要把源极和漏极完全拉上来

Now we need to pull the source and drain up completely

让栅极完全围住中间的部分，这样三面变成了四面，更好控制

Let the gate surround the middle part and turn 3 sides to 4 sides, easier to control

而且，如果我们将栅极的高度提起，在其中插入多条掺杂的半导体

What’s more, if we enlarge the height of gate and put more doped semiconductor

就能用一个大栅极去同时控制多个棒状的结构

We can control more stakes with one gate

一端作为源极，另一端作为漏极

A side is the source and the other is the drain

也就是说，将这两个电极各自分割为多个不同的部分，每个部分都单独环绕

That’s mean we divide the 2 electrodes into many parts and each part is surrounded individually

现在栅极的控制深入到了沟道内部，就能实现更多面环绕

Than the control of the gate goes deep inside the channel and implement more sides surrounding

这就是全环绕式晶体管（GAA）

This is GAA

除了这两种增大接触面积的防漏电方式

Expect these 2 ways to enlarge exposure area to stop creepage

还有改造材料的high-k和low-k方案

There are high-k and low-k ways, too

早期栅极的材料也是采用绝缘的二氧化硅

Early material of gates is insulating SiO2

你一定会问为什么不能把二氧化硅做得厚一点，这样不就不容易漏电了吗

You must ask why not make SiO2 more thick to stop creepage

实际上，一方面现在的晶体管结构都是立体的，要缩减工艺制程就最好让它薄一些

In fact, on the an hand transistors is 3D now. It’s batter to make it more thin.

另一方面加厚会导致栅极的电容降低

On the other hand thick SiO2 reduces the capacitance of the gate

当你需要晶体管导通时同样输入电压下能吸过来的电荷会减少

The charge you absorb you be down in the same inputting volt when you need the transistor to conduct

抑制沟道扩充，不利于导通

This will restrain the channel from expanding and is bad for conduction

所以人们企图采用介电常数较大的材料（例如 ）取代二氧化硅

So someone wants to use material with high dielectric constant(eg: ) to take the place of SiO2

这样在相同厚度下的栅极电容更大，有利于导通还方便栅极和氧化层的变薄

In this way the gate capacitance is larger than before in the equal thickness, which is beneficial to make gates and dioxide layer thinner

进一步缩减了工艺制程，曰high-k方案

 

reducing the process process, and this is high-k solution

但是要提升半导体芯片的工艺，除了晶体管要缩减外，另一个东西也不容忽视

But you must also focus on another problem expect reducing your transistors

那就是导线

That’s conducting wires.

本来我们的导线一般都是长度远大于横截面上的直径的

Generally speaking, our wires lengths are much more than the diameters of their cross sections

很多时候导线的电容和电感根本懒得去管

You must be too lazy to focus on the capacitances and inductances of wires in many cases

但是在芯片中长度和横截面上的直径可以不相差那么大

But the gap may be less in chips

所以不仅仅是导线的电阻，其电容和电感都是严重的干扰项

So the resistances, even capacitances and inductances are serious distractors

于是为了降低计算难度，导线需要使用介电常数低的材料

In these cases we need to use low dielectric constant material to down the calculating difficulties

那就是low-k方案

That’s low-k solution

 

 

原本沟道的形成，我们是通过控制栅极和衬底之间电压来实现的

Originally the form of channels is implemented by the control between the gate and substrate

而漏电的困境在于量子遂穿

The dilemma of creepage is because of quantum penetration

但是也有人反其道而行之，将量子遂穿设成了不同轨道的遂穿

However, someone does the opposite thing, set the quantum penetration as the penetration between different orbits

我们知道原子与原子之间形成化学键时原子轨道会有能量的升高与降低

We know the atom orbits energy will up or down when chemical bonds shape along the atoms

能量高的形成了导带，能量低的形成了价带

High energy orbits become conduction bands while the low become valence bands

中间夹杂着一条禁带

And an energy gap is between them

如果不是外界电场的暴力功能，而是利用遂穿让电子或空穴穿越两带

If you make electrons travel in these 2 bands with penetration instead of extern electronic field

实现新的控制，这就能大大提高晶体管的工作性能

in order to make new control, this will improve transistors’ working performance

greatly

此类思路制成的叫做隧穿场效应晶体管

This is tunneling field effect transistors

 

 

只是，栅极的宽度，真的需要那么小吗？集成度的提高有必要死磕这单独一个问题吗？

However, do you really need to make gate widths so small? Is it indispensable?

并不是

No

当我们把目光向上扬起，让躺平的沟道垂直于晶圆本身而坚挺中栅极中央

When we raise our gaze and lift the laying channel up, perpendicular to the wafer plane

就能在另一个维度上任意扩展栅极宽度与接触面积

You can expand the gate width and exposure area arbitrarily

神奇的垂直传输纳米片场效应晶体管（VTFET）诞生了

This is VTFET

那既然GAA里面源极和栅极可以分成多个半导体棍子而被深入包围

Since the source and draft can be divided into semiconductor stakes and be surrounded deep

我是不是也可以做得更离谱点，在一个狭窄的地基上建起智慧的高塔

I can also do more outrageously, build a wisdom tower on a narrow base

没错，这就是3D堆叠技术

Yes, what I mean is 3D stacking

绕开传统的栅极宽度要求，实现同样光刻工艺下更高的集成度

Bypassing traditional gate width requirements to achieve a higher level of integration in the same lithography process

比如，将过去FinFET和GAA的晶体管一个一个相互垂直地摆在一起

For example, place transistors of FinFET or GAA in the past vertically mutually

用一个柱子或是坑道相连，P型和N型半导体交替登场，这就是互补场效应晶体管（CFET）

connect with pillars or tunnels, PandN-type semiconductor appear alternately, and you will get CFET

2022年7月15日，中科院微电子研究所在这方面取得重大突破

On July 15, 2022, the Institute of Microelectronics of the Chinese Academy of Sciences made a major breakthrough in this regard

利用SiNx与SiO2 进行分步沟道形貌刻蚀（反正我看不懂）

SiNx and SiO2 were used for step-by-step channel morphology etching(I can’t understand what it is)

实现了混合通道互补场效应管（HF-CFET）

Implementing HF-CFET

 

 

在一些存储器例如NAND芯片上，人们大量使用以电子多少表示二进制的浮栅晶体管

In some savers such as NAND chips, people use quantity of electrons in float gate transistors to indicate binary numbers

一个个栅极围绕着沟道，而沟道则是以造柱子或挖深坑的方式实现

Gates surround channels and channels are made by building pillars and digging pits

但存储器内部可不是只有一大堆触发器在那里保存信息

But there are not only massive latches

还必须有译码等电路负责寻址等其它工作，这些电路如果和浮栅晶体管分开

There are also decoders and others to be responsible for addressing etc., if they are separated from float gate transistors

就会单独占据一块晶圆面积

They will take a single place

所以科学家们发明了阶梯式的存储电路，浮栅晶体管一层一层阶梯状排开

So scientists invented stepped saving circuits. Float gate transistors are arrayed floor by floor.

导线则是竖着与之阶梯状相连

Wires are connected to them step by step

也有人把控制电路摆在存储电路底部或分层地嵌入其中

There are also some people lay controlling circuits bottom or inside saving parts

但这样对于制作工艺，尤其是刻蚀环节的要求太高

But this process has a heigh requirement for etching

这时，中国的长江存储，就是那个搞出恐怖的232层的长江存储

Now, Yangtze River storage of China, yes, who made a 232-floors NAND chips

进行了一种奇葩的操作

does a wonderful operation

他们将存储电路和控制电路分开生产做成两块芯片

They produce saving and controlling circuits separately, making two chips

然后翻过来拼在一块儿，合二为一，这就是现在的一点小小的中国震撼——Xtacking

Then they turn these thing over and stick together, which can be thought as a little Chinese shock，Xtacking

 

 

说了这么多，相信你已经理解了为什么说芯片工艺的提升

By above words, I hope you have understood why improvements of chip process

不仅仅是对科学家发量的挑战，更是对一个国家工业体系的考验

is not only a challenge for hair inventory, more a test for a country industry system

面对政治博弈下量子遂穿的玄学难题与各种科学的高山

In the face of the metaphysical puzzle of quantum penetration in political games and variate heigh mountains of science

有人选择加大初动能，化作雄鹰翱翔而越；有人选择修改波函数，化作长波衍射而穿

Someone decides to enlarge initial moving energy, flying over it as an eagle,

While other people decide to change the wave function, transcending the barrier as a long wave

有人选择居高临下降维打击，有人选择单挑神明升维打击

Somebody will do dimension-down frighting from the heigh to the low, while some people will single gods out with dimension-up frighting

正视差距，不要怕，面对敌人不要跪，要狠狠地打

Face to the gap, but don’t be afraid. Facing the emery, don’t kneel. Instead, hit it with your force

相信自己，同志们，我们，能赢的

Believe yourself, comrades, we will win