More Verilog Features





module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
//第一位实例化
full_adder fa_inst(
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(cout[0])
);
//后99位实例化
genvar i;
generate
for(i=1;i<100;i=i+1)begin:add
full_adder fa_inst(
.a(a[i]),
.b(b[i]),
.cin(cout[i-1]),//1-1=0,*****99-1=98,99=99
.sum(sum[i]),
.cout(cout[i])
);end
endgenerate
endmodule
//全加器
module full_adder(input a,
input b,
input cin,
output sum,
output cout);
assign sum=a^b^cin;
assign cout=a&b | a&cin | b&cin;
endmodule

module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [399:0] cout_tmp;
bcd_fadd bcd_fadd_inst(
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(cout_tmp[0]),
.sum(sum[3:0])
);
assign cout = cout_tmp[400-4];
generate
genvar i;
for(i = 4; i< 400; i = i + 4)
begin :bcdadd100 // 模块名
bcd_fadd bcd_fadd_inst(
.a(a[i+3:i]),
.b(b[i+3:i]),
.cin(cout_tmp[i-4]),
.cout(cout_tmp[i]),
.sum(sum[i+3:i])
);
end
endgenerate
endmodule