FPGA:nco_fsdiv12
`timescale 1ns / 1ps
module nco_fsdiv12
#(
parameter LANE = 8,
parameter IN_WIDTH= 12
)
(
input clk,
input rst,
output [LANE*IN_WIDTH-1:0] m_axis_nco_tdata ,
output reg m_axis_nco_tvalid
);
//
genvar i;
//2047 1773 1023 0 -1024 -1773 -2047 -1773
//-1023 0 1024 1773 2047 1773 1023 0
//-1024 -1773 -2047 -1773 -1023 0 1024 1773
reg [ 2:0] cnt;
reg [IN_WIDTH-1:0] nco_initial[LANE-1:0];
//
generate
for(i=0;i<LANE;i=i+1)
begin:assign_res
assign m_axis_nco_tdata[IN_WIDTH*(i+1)-1:IN_WIDTH*i] = nco_initial[i];
end
endgenerate
//
always@(posedge clk or posedge rst)
begin
if(rst)
begin
cnt<=0;
m_axis_nco_tvalid<=0;
end
else
begin
m_axis_nco_tvalid<=1;
if(cnt<2)
begin
cnt<=cnt+1'b1;
end
else
begin
cnt<=0;
end
end
end
//
always@(posedge clk or posedge rst)
begin
if(rst)
begin
nco_initial[7]<=0;nco_initial[6]<=0;
nco_initial[5]<=0;nco_initial[4]<=0;
nco_initial[3]<=0;nco_initial[2]<=0;
nco_initial[1]<=0;nco_initial[0]<=0;
end
else
begin
case(cnt)
3'b00:begin
nco_initial[7]<=-1773;
nco_initial[6]<=-2047;
nco_initial[5]<=-1773;
nco_initial[4]<=-1024;
nco_initial[3]<= 0;
nco_initial[2]<= 1023;
nco_initial[1]<= 1773;
nco_initial[0]<= 2047;
end
3'b01:begin
nco_initial[7]<= 0;
nco_initial[6]<= 1023;
nco_initial[5]<= 1773;
nco_initial[4]<= 2047;
nco_initial[3]<= 1773;
nco_initial[2]<= 1024;
nco_initial[1]<= 0;
nco_initial[0]<=-1023;
end
3'b10:begin
nco_initial[7]<= 1773;
nco_initial[6]<= 1024;
nco_initial[5]<= 0;
nco_initial[4]<=-1023;
nco_initial[3]<=-1773;
nco_initial[2]<=-2047;
nco_initial[1]<=-1773;
nco_initial[0]<=-1024;
end
endcase
end
end
endmodule
