ICS T8431 拟路径短路且不会涉及许多组件
输入模块自动对几个
可用于详细故障排除和验证的车载信号
模块操作特性。在每个内进行测量
切片的HIU和FIU。
从IMB到现场连接器,输入模块包含大量
故障检测和完整性测试。作为一种输入设备,所有的测试都是
在非干扰模式下执行。从IMB输入的数据存储在
在HIU的每个片部分上的冗余纠错RAM。收到
数据由每个切片投票决定。所有数据传输都包含一个确认
来自接收器的响应。
在HIU和FIU之间,有一系列光学隔离的数据链路
和动力。对数据链路进行同步并监控差异。二者都
FIU和HIU都有机载温度传感器来表征
与温度相关的问题。
HIU和FIU板的电源都是冗余的,完全
仪器化和可测试。这些组件共同构成电源完整性
子系统。
模块现场输入连接到一个称为∑Δ输入的单比特ADC
环行这些电路,每个切片上每个通道一个,产生数字输出
在接通和断开之间自然转换。电路中的任何故障都会导致
输出饱和到卡在打开或关闭状态,这是自动的
检测。由于转换过程是动态的,而不是像传统的那样门控
ADC,故障得到快速诊断和定位。
通过使用∑∆电路,模块中的模拟路径短路且不会
涉及许多组件。这导致模拟故障包含在
单个切片上的单个通道,而不是导致一组八个或更多
输入失败。


The Input Module automatically performs local measurements of several
onboard signals that can be used for detailed troubleshooting and verification
of Module operating characteristics. Measurements are made within each
slice’s HIU and FIU.
From the IMB to the field connector, the Input Module contains extensive
fault detection and integrity testing. As an input device, all testing is
performed in a non-interfering mode. Data input from the IMB is stored in
redundant error-correcting RAM on each slice portion of the HIU. Received
data is voted on by each slice. All data transmissions include a confirmation
response from the receiver.
Between the HIU and FIU, there are a series of optically isolated links for data
and power. The data link is synchronized and monitored for variance. Both
the FIU and HIU have onboard temperature sensors to characterize
temperature-related problems.
The power supplies for both the HIU and FIU boards are redundant, fully
instrumented and testable. Together, these assemblies form a Power Integrity
Subsystem.
The module field input is connected to a single bit ADC known as the ΣΔ input
circuit. These circuits, one per channel on each slice, produce a digital output
that naturally transitions between on and off. Any failure in the circuit causes
the output to saturate to stuck-on or stuck-off, which is automatically
detected. As the conversion process is dynamic and not gated like traditional
ADCs, failures are rapidly diagnosed and located.
By using the Σ∆ circuit, the analog path in the Module is short and does not
involve many components. This results in analog failures being contained to a
single channel on a single slice instead of causing a group of eight or more
inputs to fail.