verilog学习记录（180题）
2023-04-03 23:32 作者:sjenixnkendnjdb | 我要投稿
0、
0. Getting Started
Practice: Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).
翻译：创建一个输出为1的电路
module top_module( output one );
assign one = 1;
endmodule
