朱佳迪攻克了1nm?

最近在各个平台都看到了朱佳迪攻克1nm的新闻

而在新闻底下

又是无尽的嘲讽

那么，这个事儿是真的吗？

百度找了一圈不管是文字 还是视频的

都是一张图

按图搜图找到的都是这个

最后，好不容易看到一个稿子，里面有文字截图

有了文字就更好搜索了

于是，终于找到了这个新闻的源头完整版截图如下

Emerging AI applications, like chatbots that generate natural human language, demand denser, more powerful computer chips. But semiconductor chips are traditionally made with bulk materials, which are boxy 3D structures, so stacking multiple layers of transistors to create denser integrations is very difficult.

However, semiconductor transistors made from ultrathin 2D materials, each only about three atoms in thickness, could be stacked up to create more powerful chips. To this end, MIT researchers have now demonstrated a novel technology that can effectively and efficiently “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip to enable denser integrations.

Growing 2D materials directly onto a silicon CMOS wafer has posed a major challenge because the process usually requires temperatures of about 600 degrees Celsius, while silicon transistors and circuits could break down when heated above 400 degrees. Now, the interdisciplinary team of MIT researchers has developed a low-temperature growth process that does not damage the chip. The technology allows 2D semiconductor transistors to be directly integrated on top of standard silicon circuits.

In the past, researchers have grown 2D materials elsewhere and then transferred them onto a chip or a wafer. This often causes imperfections that hamper the performance of the final devices and circuits. Also, transferring the material smoothly becomes extremely difficult at wafer-scale. By contrast, this new process grows a smooth, highly uniform layer across an entire 8-inch wafer.

The new technology is also able to significantly reduce the time it takes to grow these materials. While previous approaches required more than a day to grow a single layer of 2D materials, the new approach can grow a uniform layer of TMD material in less than an hour over entire 8-inch wafers.

Due to its rapid speed and high uniformity, the new technology enabled the researchers to successfully integrate a 2D material layer onto much larger surfaces than has been previously demonstrated. This makes their method better-suited for use in commercial applications, where wafers that are 8 inches or larger are key.

“Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, which is the conventional case, it won’t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogenous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top,” says Jiadi Zhu, an electrical engineering and computer science graduate student and co-lead author of a paper on this new technique.

Zhu wrote the paper with co-lead-author Ji-Hoon Park, an MIT postdoc; corresponding authors Jing Kong, professor of electrical engineering and computer science (EECS) and a member of the Research Laboratory for Electronics; and Tomás Palacios, professor of EECS and director of the Microsystems Technology Laboratories (MTL); as well as others at MIT, MIT Lincoln Laboratory, Oak Ridge National Laboratory, and Ericsson Research. The paper appears today in Nature Nanotechnology.

Slim materials with vast potential

The 2D material the researchers focused on, molybdenum disulfide, is flexible, transparent, and exhibits powerful electronic and photonic properties that make it ideal for a semiconductor transistor. It is composed of a one-atom layer of molybdenum sandwiched between two atoms of sulfide.

Growing thin films of molybdenum disulfide on a surface with good uniformity is often accomplished through a process known as metal-organic chemical vapor deposition (MOCVD). Molybdenum hexacarbonyl and diethylene sulfur, two organic chemical compounds that contain molybdenum and sulfur atoms, vaporize and are heated inside the reaction chamber, where they “decompose” into smaller molecules. Then they link up through chemical reactions to form chains of molybdenum disulfide on a surface.

But decomposing these molybdenum and sulfur compounds, which are known as precursors, requires temperatures above 550 degrees Celsius, while silicon circuits start to degrade when temperatures surpass 400 degrees.

So, the researchers started by thinking outside the box — they designed and built an entirely new furnace for the metal-organic chemical vapor deposition process.

The oven consists of two chambers, a low-temperature region in the front, where the silicon wafer is placed, and a high-temperature region in the back. Vaporized molybdenum and sulfur precursors are pumped into the furnace. The molybdenum stays in the low-temperature region, where the temperature is kept below 400 degrees Celsius — hot enough to decompose the molybdenum precursor but not so hot that it damages the silicon chip.

The sulfur precursor flows through into the high-temperature region, where it decomposes. Then it flows back into the low-temperature region, where the chemical reaction to grow molybdenum disulfide on the surface of the wafer occurs.

“You can think about decomposition like making black pepper — you have a whole peppercorn and you grind it into a powder form. So, we smash and grind the pepper in the high-temperature region, then the powder flows back into the low-temperature region,” Zhu explains.

Faster growth and better uniformity

One problem with this process is that silicon circuits typically have aluminum or copper as a top layer so the chip can be connected to a package or carrier before it is mounted onto a printed circuit board. But sulfur causes these metals to sulfurize, the same way some metals rust when exposed to oxygen, which destroys their conductivity. The researchers prevented sulfurization by first depositing a very thin layer of passivation material on top of the chip. Then later they could open the passivation layer to make connections.

They also placed the silicon wafer into the low-temperature region of the furnace vertically, rather than horizontally. By placing it vertically, neither end is too close to the high-temperature region, so no part of the wafer is damaged by the heat. Plus, the molybdenum and sulfur gas molecules swirl around as they bump into the vertical chip, rather than flowing over a horizontal surface. This circulation effect improves the growth of molybdenum disulfide and leads to better material uniformity.

In addition to yielding a more uniform layer, their method was also much faster than other MOCVD processes. They could grow a layer in less than an hour, while typically the MOCVD growth process takes at least an entire day.

Using the state-of-the-art MIT.Nano facilities, they were able to demonstrate high material uniformity and quality across an 8-inch silicon wafer, which is especially important for industrial applications where bigger wafers are needed.

“By shortening the growth time, the process is much more efficient and could be more easily integrated into industrial fabrications. Plus, this is a silicon-compatible low-temperature process, which can be useful to push 2D materials further into the semiconductor industry,” Zhu says.

In the future, the researchers want to fine-tune their technique and use it to grow many stacked layers of 2D transistors. In addition, they want to explore the use of the low-temperature growth process for flexible surfaces, like polymers, textiles, or even papers. This could enable the integration of semiconductors onto everyday objects like clothing or notebooks.

“This work made an important progress in the synthesis technology of monolayer molybdenum disulfide material,” says Han Wang, the Robert G. and Mary G. Lane Endowed Early Career Chair and Associate Professor of Electrical and Computer Engineering and Chemical Engineering and Materials Science at the University of Southern California, who was not involved with this research. “The new capability of low thermal budget growth on an 8-inch scale enables the back-end-of-line integration of this material with silicon CMOS technology and paves the way for its future electronics application.”

This work is partially funded by the MIT Institute for Soldier Nanotechnologies, the National Science Foundation Center for Integrated Quantum Materials, Ericsson, MITRE, the U.S. Army Research Office, and the U.S. Department of Energy. The project also benefitted from the support of TSMC University Shuttle.

chatGTP翻译如下

新兴的人工智能应用，如生成自然人类语言的聊天机器人，需要更密集、更强大的计算机芯片。但传统上，半导体芯片是由立方体3D结构的块材料制成的，因此堆叠多个层次的晶体管以创建更密集的集成是非常困难的。

然而，由超薄2D材料制成的半导体晶体管，每个只有大约三个原子厚度，可以堆叠起来创建更强大的芯片。为此，MIT的研究人员现已展示了一种新颖技术，可以有效地和高效地“生长”多层二维过渡金属二硫化物（TMD）材料直接在完全制造好的硅片上，以实现更密集的集成。

将2D材料直接生长在硅CMOS晶圆上一直是一个巨大的挑战，因为这个过程通常需要约600摄氏度的温度，而硅晶体管和电路在加热至400摄氏度以上时可能会损坏。现在，MIT的跨学科研究团队开发了一种不会损坏芯片的低温生长过程。该技术可使2D半导体晶体管直接集成在标准硅电路上。

过去，研究人员在其他地方生长2D材料，然后将它们转移到芯片或晶圆上。这经常会导致缺陷，从而影响最终设备和电路的性能。此外，在晶圆规模上平滑转移材料变得极为困难。相比之下，这种新方法在整个8英寸晶圆上生长出了一层光滑、高度均匀的材料。

新技术也能够显著缩短生长这些材料所需的时间。虽然之前的方法需要一天以上才能生长一层2D材料，但新方法可以在一个小时内在整个8英寸晶圆上生长出一层TMD材料的均匀层。

由于其快速的速度和高度均匀，因此新技术使研究人员成功地将2D材料层集成到比先前曾经展示过的更大的表面上。这使得他们的方法更适合商业应用，其中8英寸或更大的晶圆至关重要。

电气工程和计算机科学研究生和本研究新技术的共同作者之一朱佳迪表示：“使用2D材料是提高集成电路密度的有力方式。我们正在做的就像建造多层楼房。如果只有一个楼层，也就是传统情况下，它不会容纳很多人。但是有了更多的楼层，建筑物将容纳更多的人，从而实现惊人的新事物。由于我们正在进行异质集成，因此硅是第一层，然后可以将许多层2D材料直接集成在其上。”

该论文的共同作者还包括本文的共同作者Park Ji-Hoon、电气工程和计算机科学（EECS）教授、电子研究实验室的成员孔晶教授以及微系统技术实验

有自媒体让国人反思，自然也有说他不是中国人的。

但，他的脸书上，确实写着自己是江苏南京人。

当然，现在可能已经不是了。

怎么说呢？

对世界来说，这是个好事儿。

但是用来说国内学术环境不行也大可不必。

记得大头鹰直播的时候，有个在海外的小姐姐也说了，

在外面也是一个鸟样。

找到链接了的话，我再补上。