单元CPU模块DS200TCCAG1B调节器工控卡件PLC/DCS备件系统
产品详情资料：
注：有关供应商提供的芯片和其他第三方电路板组件的更多信息，请参阅相关文档附录中标题为“适用的非摩托罗拉文档”的部分。下图（表1-7）中所指的DRAM均为奇偶保护型DRAM，与MVME162LX 200/300系列中的许多电路板一起提供。本指南的MCchip一章介绍了此映射所概述的芯片寄存器。对于带有ECC保护DRAM的电路板，请参阅下表1-10和本指南的MCECC芯片章节。注意：MVME162LX 200/300系列上的IPIC芯片***多支持四个工业封装（IP）接口，***为IP_a到IP_d。200/300系列本身可容纳两个IP：IP_a和IP_b。在以下映射中，适用于IP_c和IP_d的段未在MVME162LX 200/300系列中使用。IPIC控制和状态寄存器（CSR）汇总如表1-9所示。CSR可以以字节、单词或长单词的形式访问。它们不应作为行访问。表中以字节表示。注意：下表（表1-10）中所指的DRAM均为ECC保护型DRAM，即MVME162LX 200/300系列中大多数主板所提供的DRAM类型。本指南的MCECC一章介绍了此映射所概述的芯片寄存器。对于具有奇偶校验保护DRAM的电路板，请参见上文表1-7和本指南的MCchip一章。
产品英文详情料:
Note For further information on the vendor-supplied chips and other third-party board components, see the section entitled “Applicable Non-Motorola Documentation” in the Related Documentation Appendix.The DRAM referred to in the following map (Table 1-7) is all parity-protected, the type of DRAM supplied with many of the boards in the MVME162LX 200/300 Series. The chip registers outlined by this map are covered in the MCchip chapter of this Guide. For the boards with ECC-protected DRAM see below, Table 1-10, and the MCECC chip chapter of this Guide.Note The IPIC chip on the MVME162LX 200/300 Series supports up to four IndustryPack (IP) interfaces, designated IP_a through IP_d. The 200/300 Series itself accommodates two IPs: IP_a and IP_b. In the maps that follow, the segments applicable to IP_c and IP_d are not used in the MVME162LX 200/300 Series.A summary of the IPIC Control and Status Registers (CSRs) is shown in Table 1-9. The CSRs can be accessed as bytes, words, or longwords. They should not be accessed as lines. They are shown in the table as bytes.Note The DRAM referred to in the following map (Table 1-10) is all ECC-protected, the type of DRAM supplied with most of the boards in the MVME162LX 200/300 Series. The chip registers outlined by this map are covered in the MCECC chapter of this Guide. For the boards with parity-protected DRAM see above, Table 1-7, and the MCchip chapter of this Guide.
