《计算机组成原理》习题及答案

2022-04-03 08:44 作者:莎莉娜的仙子伊布 0人读过 | 我要投稿

注：本教材为William的《计算机组织与结构》——性能设计第九版，唐书和白书可供参考

Chapter1-2

1. Gordon Moore observed that the number of transistors that could be put on a single chip was doubling every ________ months in the 1970s. A. 24 B. 12 C. 18 D. 15

2._____ gave the conception of stored-program.

A. Bill Gates B. Gordon Moore C. John von Neumann D. John Mauchly

3. In each instruction, specifies the operation to be performed.

A. address field B. operand C. next instruction reference D. opcode

Chapter 3

1. PC means _________.

A. personal computer B. programming controller C. program counter D. portable computer

2. PC holds _______________ .

A. address of next instruction B. next instruction C. address of operand D. operand

3. At the end of fetch cycle, MAR holds _____.

A. address of instruction B. instruction C. address of operand D. operand

4. Interrupt process steps are __________.

A. suspending , resuming , branching & processing B. branching , suspending , processing & resuming

C. suspending , branching , processing & resuming D. processing , branching , resuming & suspending

5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .

A. 0 to n-1 B. 1 to n C. 0 to 2n-1 D. 1 to 2n

6. The length of address is 32 bits, so addressing range (or the range of address) is ________________.

A. 4G B. from –2G to 2G C.4G-1 D. from 1 to 4G

7. There are three kinds of BUS. Which does not belong to them?

A. address bus B. system bus C. data bus D. control bus

8. In the simplest instruction processing form, it consists of two cycles: _____________.

A. fetch and indirect B. fetch and execute C. indirect and execute D. fetch and interrupt

9. The control lines are used to control the access to and the use of the data and address lines. Typical control signals include the following: _____________.

A. read and write B. interrupt request and acknowledge signal C. clock D. A, B and C

10. At the end of fetch cycle, IR holds .

A instruction B operand C address of operand D address of instruction

11. ____________register holds address of next instruction ?

A. MAR B. MBR C. PC D. IR

12. An unsigned binary integer is ________ bits, so it can represent an integer between 0~4G-1.

A. 64 B. 32 C. 16 D. 8

13. There are three levels of BUSes in modern computer system. ________ doesn’t belong to them?

A. expansion bus B. system bus C. data bus D. high-speed bus

14. Which is not true in the following description about BUS？

A. a bus is a communication pathway connecting two or more devices B. Usually broadcast

C. The number of lines is the width of the bus D. More than one module may control bus at one time

Chapter4 Cache

一.Select the best answer based on this course.

1. The computer memory system refers to _________

A.RAM B. ROM C. Main memory D.Register , main memory, cache, external memory

2. If the word of memory is 16 bits, which the following answer is right?

A. The address width is 16 bits B. The address width is related with 16 bits

C.The address width is not related with 16 bits D. The address width is not less than 16 bits

3. The characteristics of internal memory compared to external memory

A. Big capacity, high speed, low cost B. Big capacity, low speed, high cost

C. small capacity, high speed, high cost D. small capacity, high speed, low cost

4．On address mapping of cache, any block of main memory can be mapped to any line of cache, it is ___________ .

A. Associative Mapping B. Direct Mapping C. Set Associative Mapping D. Random Mapping

5. Cache’s write-through polity means write operation to main memory _______.

A. as well as to cache B. only when the cache is replaced

C. when the difference between cache and main memory is found D. only when direct mapping is used

6. Cache’s write-back polity means write operation to main memory ______________.

A. as well as to cache B. only when the relative cache is replaced

C. when the difference between cache and main memory is found D. only when using direct mapping

7. On address mapping of cache, the data in any block of main memory can be mapped to fixed line of cache, it is _ ____.

A. associative mapping B. direct mapping C. set associative mapping D. random mapping

8. On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is ___________.

A. associative mapping B. direct mapping C. set associative mapping D. random mapping

9. Computer memory is organized into a hierarchy. At the highest level are the ___________.

A. registers B. cache C. main memory D. external memory

10. On address mapping of cache, the data in any block of main memory can be mapped to ____ of cache, it is direct mapping .

A. any line B. fixed line C. fixed set any line D. A and B

11. The characteristics of external memory compared to internal memory are _______ .

A.Big capacity, high speed, low cost B. Big capacity, low speed, low cost

C. small capacity, high speed, high cost D. small capacity, high speed, low cost

12. Write _____ policy can result in memory write bottle-neck.

A. back B. through C. from D. to

13.A 16KByte cache has a line size of four 32-bit words, the number of line is .

A 210 B 10 C 28 D 8

14. If the address-length of memory is 16 bits, which the following answer is NOT right ? .

A.The addressable unit is 16 bits B.The addressing range is 216

C.The maxmum possible memory capacity is determined D.The addressable unit is not related with 16 bits

15. Suppose that the word from location X in memory can be mapped any line in the cache, this mapping function is called _____________.

A. associative Mapping B. direct Mapping

C. set Associative Mapping D. random Mapping

16. The simplest technique is called _____________.Using this technique, all write operations are made to main memory as well as to the cache.

A. write-back B. write-through

C. write-invalidate D. write-update

二.计算题

A four-way set-associative cache has 4K bytes and a line size of four bytes. The 4-Gbyte main memory is byte addressable. Questions:

1. Show the mapping format of main memory addresses.

2. Where in the cache is the word from memory location ABCDE8F8H mapped?

3. What are the addresses of the other words stored along with the location ABCDE8F8H?

4. Where in the memory is the data from cache set number D6H and tag value 13579AH?(when write to memory)

Chapter 5 Internal Memory

一、选择题

1. Which type of memory is volatile?

A.ROM B. E2PROM C. RAM D. flash memory

2. Which type of memory has 6-transistor structure?

A. DRAM B. SRAM C. ROM D. EPROM

3. Using hamming code to one-bit error.

A. detect and correct B. detect C. correct D. none of all

4. Flash memory is .

A. read-only memory B. read-mostly memory C. read-write memory D. volatile

5. Which answer about internal memory is not true?

A. RAM can be accessed at any time, but data would be lost when power down..

B. When accessing RAM, access time is non-relation with storage location.

C. In internal memory, data can’t be modified.

D. Each addressable location has a unique address

6. we use ____________to detect and correct one-bit error of main memory.

A. hamming code B. ASCII C. Parity code D. none of all

7. If main memory capacity is 2G-Byte, the length of the effective address code is _______.

A. 24-bit B. 32-bit C. 28-bit D. 31-bit

8. Using hamming code, syndrome word is 0110 means is wrong.

A the data of hamming code’s position 10 B the data of data bit 6

C the data of hamming code’s position 6 D the data of data bit 10

9. Which type of memory contains a permanent pattern of data that cannot be changed? .

A SRAM B DRAM C EEPROM D PROM

10. Which is the nonvolatile semiconductor memory? _____________.

A. SRAM B. CD-ROM C. FLASH D. DRAM

11. In the following description, which is NOT right? _____________.

A. SRAM is faster than DRAM B. DRAM needs periodic charge refreshing circuit

C. DRAM is slower than Flash D. ROM does not require power supplied continuously

12. Which type of memory is nonvolatile?

A. Register B. DRAM C. cache D. flash memory

二.计算题

1. For 8-bit word 00111001, suppose when read word from memory ,the check bits are calculated is 1101. Questions:

1) What is the data read from memory?

2) What is hamming code to be stored in memory？

3) What is hamming code read from memory？

2. Hamming code 0011 0110 1111 is just read from main memory. Please write the check and correct error processing with the principle of Hamming SEC code.

Chapter 6 External Memory

1. Which of the following statements about hard disk is false?___________

A. Minimum block size is one sector

B. Data is striped by cylinder

C. Rotational latency is the time for head to wait for data to rotate under the head

D. The aim of formatting disk is to add additional information to mark tracks and sectors which is available to user

2. Which of the following statements about Winchester hard disk is false?___________

A. During read/write, head is stationary, platter rotates. B. There is one head per platter(盘片) of hard disk .

C. Heads are joined and aligned. D. Heads fly on boundary layer of air as disk spins.

3. Which of the following statements about contemporary read head of hard disk is not true?____________

A. It is a partially shielded magneto resistive (MR) sensor .

B. Coil is the same for read and write.

C. The principal is electrical resistance depends on direction of magnetic field.

D. Compared with traditional read head, it can achieve high frequency operation.

4.On a movable head system, the time it takes for the beginning of the sector to rotate under the head is known as .

A. rotational delay B. seek time C. transfer time D. access time

5. The time for the head of hard disk move to the correct track is ____________.

A. rotational delay B. seek time C. transfer time D. access time

6. In RAID, parity means that more disk’s capacity is used_____.

A. to enlarge capacity of available data in disk system B. to enable the recovery of data lost due to a disk failure

C. to find and correct the read/write errors D. to improve I/O request rate of system

7. In RAID, REDUNDANT means that more disks are used for _____________.

A. enlarging capacity of disk system B. improving transfer rate of system

C. finding and correcting the read/write error D. improving reliability of disk system

8. Which RAID level does not make use of parity(奇偶校验) information to recover data?

A. RAID 4 B. RAID 3 C. RAID 1 D. RAID 5

9. In RAID, redundant disk capacity is used to store _______, which is used to recover data in case of a disk failure.

A. user data B.disk information C. operating system D. parity information

10. RAID level(s)_________make(s) use of an independent access technique for the purpose of high I/O request rate.

A. 2 B. 3 C. 4 D. all

11.RAID levels 2 and 3 make use of a _______technique for the purpose of high data transfer rate.

A. parallel access B. random access C. direct access D. indepedent accessn

12. Each logical strip is mapped to two separate physical disk In _________.

A. RAID 1 B. RAID 2 C. RAID 3 D. RAID 4

13. Assume a 10-drive RAID configuration. In RAID1 level, storage density is _______

A. 90% B. 80% C. 60% D. 50%

14. Compared with RAID4, the advantage of RAID5 is _______

A. Each disk operates independently B. Large strips

C. Parity is striped across all disks D. Data on failed drive can be reconstructed

15. The main ID field of a typical hard disk is _____________

A. track#, sector#, head# B. cylinder#, head#, sector#

C. sector#, side#, track# D. sector#, track#, head#

16. When a processor accesses disk, it must know three parameters: _____________.

A. side, head and track B. side, sector and cylinder

C. cylinder, sector and track D. side, sector and platter

Chapter 7 Input/Output

一、单选题

1. “When the CPU issues a command to the I/O module, it must wait until the I/O operation is complete”. It is programmed I/O , the word “wait” means ___________________.

A. the CPU stops and does nothing B. the CPU does something else

C. the CPU periodically reads & checks the status of I/O module D. the CPU wait the Interrupt Request signal

2. To save PSW, PC and remainder onto stack, why the operations of restoring them is reversed? Because the operations of stack are __________.

A. first in first out B. random C. last in first out D. sequenced

3. Using stack to save PC and remainder, the reason is ____________________ .

A. some information needed for resuming the current program at the point of interrupt

B. when interrupt occurs, the instruction is not executed over, so the instruction at the point of interrupt must be executed once again C. the stack must get some information for LIFO D. the start address of ISR must transfer by stack

4. The signals of interrupt request and acknowledgement exchange between CPU and requesting I/O module. The reason of CPU’s acknowledgement is ________________

A. to let the I/O module remove request signal B. to let CPU get the vector from data bus

C. both A and B D. other aims

5. In DMA , the DMA module takes over the operations of data transferring from CPU, it means _____________

A. the DMA module can fetch and execute instructions like CPU does

B. the DMA module can control the bus to transfer data to or from memory using stealing cycle technique

C. the DMA module and CPU work together(co-operate) to transfer data into or from memory

D. when DMA module get ready, it issues interrupt request signal to CPU for getting interrupt service

6. Transfer data with I/O modules, 3 types of techniques can be used. Which doesn’t belong to them? _______.

A. Interrupt-driven I/O B. Programmed I/O C. Direct I/O access D. DMA

7. Which I/O technique should be taken to output a data block of some sectors to hard disk? ___________

A. Interrupt-driven I/O B. Programmed I/O C. Direct I/O access D. DMA

8. Which I/O technique should be taken to input a word from keyboard? __________

A. Interrupt-driven I/O B. Programmed I/O C. DMA D. Direct I/O access

9. Comparing with interrupt-driven I/O, DMA further raises the usage rate of CPU operations, because __________

A. it isn’t necessary for CPU to save and restore scene B. it isn’t necessary for CPU to intervene the dada transfer

C. it isn't necessary for CPU to read and check status repeatedly D. both A and B

10. Transfer data with I/O modules, 3 types of techniques can be used. Which isn’t necessary for CPU to intervene the dada transfer? ____________.

A. Interrupt-driven I/O B. Programmed I/O C. Direct I/O access D. DMA

11. In simple interrupt processing, how does the processor get the interrupt number? ___________

A. Issue acknowledgement of interrupt B. Load new PC value based on interrupt

C. Restore process state information D. Receive interrupt request signal

12. Having checked the Interrupt Request signal from I/O module, CPU sends back Interrupt Acknowledgment signal to the module to __________.

A. let the module remove the Request signal B. let the module put the “vector” on data bus

C. let the module send PC value to CPU D. A and B

13. Comparing with programmed I/O, interrupt-driven I/O further raises the usage rate of CPU operations, because __________

A. it isn’t necessary for CPU to save and restore scene B. it isn’t necessary for CPU to intervene the dada transfer

C. it isn’t necessary for CPU to read and check status repeatedly D. both A and B

14. In DMA, when does DMA module issue interrupt request signal to CPU?

A. before DMA module transfers a block data B. after DMA module finishes a block data transfer

C. before DMA module seizes to use bus D. after DMA module ends to seize bus

15. The address of the top of stack is stored in register. A. PC B. AC C. SP D. PSW

16. The interrupt request signal is send from to .

A. CPU, I/O module B. I/O module,CPU C. CPU,memory D. memory,CPU

二.简答题

1. In the interrupt processing, the CPU saves information of current program to stack for resuming it. What is the important information?

2. In the interrupt processing, when can CPU send an acknowledgement signal to requesting I/O module for the interrupt request? Why does CPU send the acknowledgement signal?

3. In the interrupt processing, when will CPU respond to the interrupt? Where does the CPU save the PC,PSW and remainder of current program ?

Chapter10 Computer Arithmetic

1. Suppose the length of two’s complement is 5 bits, which arithmetic operation brings OVERFLOW?

A. 5+8 B. (-8)+(-8) C. 4-(-12) D.15-7

2. Overflow occurs sometimes in ______arithmetic operation. A. add B. subtract C. add and subtract D. multiply

3. In twos complement, two positive integers add, when does overflow occur?

A. There is a carry B. Sign bit of result is 1 C. There is a carry, and sign bit of result is 0 D. Can’t determine

4. The 8-bit twos complement 1001 0011 is stored in 16-bit. It’s equal to____.

A.1000 0000 1001 0011 B. 0000 0000 1001 0011 C.1111 1111 1001 0011 D.1111 1111 0110 1101 11

5. The 8-bit twos complement 0001 0011 is stored in 16-bit. It’s equal to ____.

A. 1000 0000 1001 0011 B. 0000 0000 0001 0011 C. 1111 1111 0001 0011 D. 1111 1111 1110 1101

6. Booth’s algorithm is used for Twos complement ______. A. addition B. subtraction C. multiplication D. division

7. The range of n-bit twos complement representation is ___________.

A. 0 ~ 2n-1 B. -2n-1 ~ 2n-1 C. -2n-1 ~ 0 D. -2n-1 ~ 2n-1-1

8. The main functions of ALU are ?

A. Logic B. Arithmetic C. Logic and arithmetic D. Only addition

9. Which is not true?

A. Subtraction can not be finished by adder and complement circuits in ALU

B. Carry and overflow are not same

C. In twos complement, the negation of an integer can be performed with the following rules: bitwise not (including the sign bit), and add 1.

D. In twos complement, addition is normal binary addition, but monitor sign bit for overflow

Chapter12 instruction set:特点和功能

1. In instruction, the number of addresses is 0, the operand(s)’address is implied, which is(are) in_______.

A. accumulator B. program counter C. top of stack D. any register

2. The address of the top of stack is stored in ______________.

A. PC B. Accumulator C. SP D. Base Register

3. In an instruction, the number of addresses is 2, one address does double duty of_________.

A. a result and the address of next instruction B. an operand and a result

C. an operand and the address of next instruction D. two closed operands

4. The address is known as a type of data, because it is represented by __________.

A. a number of floating point B. a signed integer C. an unsigned integer D. a number of hexadecimal

5. A branch instruction performed by CPU is to update ____.

A. MBR to contain the instruction B. Program counter to contain the address of next instruction

C. MAR to contain the address of current instruction D. IR to contain the instruction that just fetched from memory

6. Which element of an Instruction can’t be implicit? ______

A. Operation code B. Source Operand reference C. Result Operand reference D. Next Instruction Reference

7. In each machine instruction, ______specifies the operation to be performed (e.g. ADD, I/O)

A. Operation code B. Source Operand reference C. Result Operand reference D. Next Instruction Reference

8. Consider a machine-language instruction CALL X, which stands for calling procedure at location X. If the return address is saved on the top of stack, the saved location is pointed by ___________.

A. SP B. PC C. MAR D. MBR

Chapter 13 Addressing Mode

一、单选题

1. In base-register addressing mode, the address of operand is equal to__________.

A. The content of base-register plus displacement B. The content of index-register plus displacement

C. The content of program counter plus displacement D. The content of AC plus displacement

2. The address of operand is in the instruction, it is_________ .

A. Direct addressing mode B. Register indirect addressing mode

C. Stack addressing mode D. Displacement addressing mode

3. Compared with indirect addressing mode , the advantage of register indirect addressing mode is________.

A. Large address space B. Multiple memory reference C. Limit address space D. Less memory access

4. With base-register ADDRESSING , the ______________ register can be used.

A. BASE B. INDEX C. PC D. ANY

5. The disadvantage of INDIRECT ADDRESSING is ____________.

A. large addressing range B. no memory access

C. more memory access D. large value range

6. Which is not an advantage with REGISTER INDIRECT ADDRESSING?

A. just one times of operand’s access B. large memory space

C. large value range D. no memory reference

7. The disadvantage of IMMEDIATE ADDRESSING is ___________.

A. limited address range B. more memory access

C. limit value range D. less memory access

8. The advantage of IMMEDIATE ADDRESSING is ___________.

A. limited address range B. more memory access

C. limit value range D. no memory access to fetch operand

9. Indirect addressing mode is viewed as the worst because it _________

A. has a large address range B. can access flexibly memory

C. wastes a lot of memory access time D. can’t get standard data

10. The address of operand is in _____________, it is direct addressing mode.

A. the instruction B. the register R

C. the main memory D. virtual memory

11. Compared with register indirect addressing mode, the disadvantage of indirect addressing mode is___________.

A. Large address space B. Multiple memory reference

C. Limit address space D. Less memory access

12. Which addressing mode does not belong to displacement addressing? ____.

A. relative addressing B. base-register addressing

C. index addressing D. register indirect addressing

13. In register indirect addressing, the effective address of operand is stored in __ __.

A. register B. main memory C. instruction D. PC

14. Which addressing mode is similar to direct addressing? The only difference is that the address field does not refer a main memory address. ___________.

A. Register B. Displacement

C. Register indirect D. stack

15. The REGISTER ADDRESSING has very less address space, but it has (is) _________________.

A. very less value range B. very fast

C. more memory access D. complex address calculation

二.简答题（共3题，40分）

1.LOAD AC,(1011H):Transfer the operand pointed by the content of memory location 1011H to AC.

Which addressing mode is included in this instruction? Please draw the figure of its addressing mode.

2.According the following figure, if ① is the address of operand, which addressing mode is used? Complete the figure.

3. The instruction: ADD [BX].

—Operand pointed by the content of register BX is added to register AX, that means (AX)+((BX))->AX

Which addressing mode is in this instruction? Please draw the figure of its addressing mode.

Chapter 14 Processor Structure and Functions

1. An instruction cycle includes indirect cycle, because it has ______.

A. indirect addressing mode B. less memory access C. complex arithmetic D. variable instruction format

2. The indirect sub-cycle is occurred _____________ .

A. before fetch sub-cycle B. after execute sub-cycle

C. after interrupt sub-cycle D. after fetch sub-cycle and before execute sub-cycle

3. In indirect sub-cycle, CPU must ___________.

A. fetch operand or store result B. fetch operand’s address from memory

C. fetch next instruction from memory D. nothing

4. In general, which register is used for relative addressing? _________

A. SP B. IR C. BR D. PC

5. The Memory Address Register connects to BUS .

A. system B. address C. data D. control

6. The Memory Buffer Register links to ________ BUS.

A. system B. address C. data D. control

7. After Indirect cycle , there is a ______________ cycle .

A. Fetch B. Indirect C. Execute D. Interrupt

8. If interrupt pending ,the Interrupt cycle is __________ ______ Execute cycle .

A. always after B. never after C. sometime after D. maybe before

9. The correct instruction cycle sequence is _________________ .

A. Fetch , Indirect , Execute and Interrupt B. Fetch , Execute , Indirect and Interrupt

C. Fetch , Indirect , Interrupt and Execute D. Indirect , Fetch , Execute and Interrup

10. The aim of the indirect cycle is to get __________________.

A. an operand B. an instruction C. an address of an instruction D. the address of an operand

11.Which is not in the ALU? ______

A. shifter B. adder C. complementer D. accumulator

12.The registers in the CPU is divided _____registers and ________registers .

A. general purpose , user-visible B. user-visible , control and status

C. data , address D. general purpose , control and status

13. After the information flow of fetch sub-cycle, the content of MBR is_____________.

A. operand B. address of instruction C. instruction D. address of operand

14. After the information flow of indirect sub-cycle, the content of MBR is_____________.

A.oprand B.address of instruction C. instruction D. address of operand

15. In _____________, CPU fetches operand’s address from memory?

A. indirect sub-cycle B. fetch sub-cycle C. execute sub-cycle D. interrupt sub-cycle

16. At the end of __________ ,the content of MBR is address of operand.

A. indirect sub-cycle B. fetch sub-cycle C. execute sub-cycle D. interrupt sub-cycle

17. At the end of _________ , the content of MBR is instruction.

A. indirect sub-cycle B. fetch sub-cycle C. execute sub-cycle D. interrupt sub-cycle

18. Instruction pipeline can improve(提高)_____________________.

A. processing speed of program B. accessing speed of memory

C. accessing speed of I/O D. accessing speed of RAID

19.In indirect cycle, what operation will be executed?

A fetch an instruction from memory B fetch an address of operand from memory

C fetch an operand from memory D all of answers are not true

20. After fetch cycle, MBR holds ____.

A operand B instruction C address of instruction D address of operand

21. Why is the branch instruction the worst to limit instruction pipeline? __________.

A. the number of its pipeline stages is larger B. its instruction cycles is complex

C. it can invalidate several instruction fetches D. the number of its pipelines is large

22. Which is the worst instruction to limit instruction pipeline?

A. ADD AX, X B. JUMP X C. RETURN D. BRZ X

23. The worse factor that limits the performance of instruction pipeline is _________________.

A.conditional branch delaying the operation of target address B. the stage number of pipeline can’t exceed 6

C. two’s complement arithmetic too complex D. general purpose registers too few

24.The worst factor to limit instruction pipeline is __________.

A. The number of stages B. the number of instruction C. the conditional branch instruction D. the number of pipelines

Chapter 15 RISC

1. RISC rejects ______.
A. few, simple addressing modes B. a limited and simple instruction set

C. few, simple instruction formats D. a few number of general purpose registers

2. RISC rejects ______.

A.a large number of general-purpose registers B. indirect addressing

C. a single instruction size D. a small number of addressing mode

3. Which is NOT a characteristic of RISC processor.

A. a highly optimized pipeline. B. Register to register operations

C. a large number of general-purpose registers D. a complexed instruction format

4. Which is NOT a characteristic of RISC processor? ______.

A. indirect addressing mode B. register to register operations

C. a single instruction size D. simple instruction format

Chapter 17 Parallel Processing

一、单选

1.In MESI protocol, if the initiating cache’s state is exclusive, the snooping cache’s state is .

A. modified B. exclusive C.invalid D. shared

2. In multi-processor organizations, the method of sharing Memory is called .

A.loosely coupled B.cluster C.tightly coupled D. symmetric

3. In MESI protocol, a read miss occurs in the local cache. The beginning state: initial is invalid, snoopy is exclusive. After initiating CPU read the data, the ending state is .

A. initial is exclusive, snoopy is invalid B. initial is shared, snoopy is shared

C. initial is modified, snoopy is shared D. initial is modified, snoopy is invalid

4. In MESI protocol, a write miss occurs in the local cache. After initiating CPU writes the data, the snooping cache’s state is .

A. modified B. shared C. invalid D. modified or shared or invalid or exclusive

5. is not in SMP’s properties.

A. Using shared memory B. Using 2 or more same or similar processors.

C. Using 2-level local caches D. Using high performance network-linkage

6. Symmetric Multi-Processor (SMP) system is tightly coupled by _______.

A. high-speed data-link and distributed memory B. shared RAIDs and high-speed data-link

C. distributed caches and shared memory D. interconnect network and distributed memory

7. The SMP means __________.

A. Sharing Memory Processes B. Split Memory to Parts

D. Stack and Memory Pointer D. Symmetric Multi-Processor

8. The “MESI” means states of ____________ .

A. Modified, Exclusive, Stored and Inclusive B. Modified, Expected, Shared and Interrupted

C. Modified, Exclusive, Shared and Invalid D. Moved, Exchanged, Shared and Invalid

9. The protocol “MESI” is also called __________.

A. write back policy B. write-update protocol

C. write-invalidate protocol D. write through policy

二、简答题

In multi-processor systems, MESI protocol is used to solve the problem of cache coherence.

Questions:

(1) This is the case of ________________.

(2) Please complete this figure.

(3) With this case, please fill best answers into following table

Chapter19 Control Unit

一、Select the best answer based on this course

1. Control unit use some input signals to produce control signals that open the gates of information paths and let the micro-operations implement. Which is NOT the input signals of control unit?

A. clock and flags B. instruction register C. interrupt request signal D. memory read or write

2. Control unit use some output signals to cause some operations. Which is not included in the output signals?

A. signals that cause data movement B. signals that activate specific functions(e.g. add/sub/…)

C. flags D. read or write or acknowledgement

二、Show all the micro-operations and control signals for the following instruction:

1. ADD AX, X;

—The contents of AC adds the contents of location X, result is stored to AC.

2. MOV AX, [X];

—Operand pointed by the content of location X is moved to AX, that means ((X))->AX

—[ ] means indirect addressing.

3. ADD AX, [BX];

—Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX

—[ ] means register indirect addressing.

Chapter1-2

Chapter 3

Chapter4 Cache

一.Select the best answer based on this course.

二.计算题

A four-way set-associative cache has 4K bytes and a line size of four bytes. The 4-Gbyte main memory is byte addressable. Questions:

1. Show the mapping format of main memory addresses.

2. Where in the cache is the word from memory location ABCDE8F8H mapped?

3. What are the addresses of the other words stored along with the location ABCDE8F8H?

4. Where in the memory is the data from cache set number D6H and tag value 13579AH?(when write to memory)

Chapter 5 Internal Memory

Chapter 6 External Memory

Chapter 7 Input/Output

一、单选题

二.简答题

1. In the interrupt processing, the CPU saves information of current program to stack for resuming it. What is the important information?

Answer：PSW, PC and Remainder

2. In the interrupt processing,

（1）when can CPU send an acknowledgement signal to requesting I/O module for the interrupt request?

Answer：The CPU finishes execution of the current instruction before responding to the interrupt.

The CPU tests & makes sure of an interrupt , and sends an acknowledgment signal to this module.

（2）Why does CPU send the acknowledgement signal?

Answer：① allows the module to remove its interrupt signal

② to sends interrupt number to CPU

3. In the interrupt processing,

（1）when will CPU respond to the interrupt?

Answer：The CPU finishes execution of the current instruction before responding to the interrupt

（2）Where does the CPU save the PC,PSW and remainder of current program ?

Answer：Stack

Chapter10 Computer Arithmetic

Chapter12 instruction set:特点和功能

Chapter 13 Addressing Mode

一、单选题

Chapter 14 Processor Structure and Functions

Chapter 15 RISC

Chapter 17 Parallel Processing

一、单选

Chapter19 Control Unit

标签：

《计算机组成原理》习题及答案

一、单选题

二.简答题

Chapter10 Computer Arithmetic

一、单选题

二.简答题（共3题，40分）

一、单选题

二.简答题

Chapter10 Computer Arithmetic

一、单选题