VERILOG-A二进制码转温度计码译码器代码

最近项目需要用到一个二进制码转温度计译码的模块，放在Virtuoso中仿真使用

但是一开始我只会写Verilog代码，而Verilog代码只能用AMS仿真，比较麻烦

所以我自己尝试完成了一个Verilog-A描述的二进制转温度计码译码器

输入的高6位采取温度计码译码，低两位直接二进制译码

模块的Verilog描述如下:

module decoder

(

    input               clk,

    input               rst_n,

    input               [7:0]indata,

    output              [1:0]bin_data,

    output  reg         [62:0]therm_data

);

reg         [7:0]data;

   

always@(posedge clk or negedge rst_n)

begin

    if(~rst_n)

    begin

        data <= 8'b0;

    end

    else begin

        data <= indata;

    end

end

assign bin_data[1:0] = data[1:0];

always@(*)

begin

    case(data[7:2])

     6'd0:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00000000;

     6'd1:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00000001;

     6'd2:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00000011;

     6'd3:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00000111;

     6'd4:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00001111;

     6'd5:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00011111;

     6'd6:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_00111111;

     6'd7:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_01111111;

     6'd8:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000000_11111111;

     6'd9:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000001_11111111;

    6'd10:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000011_11111111;

    6'd11:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00000111_11111111;

    6'd12:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00001111_11111111;

    6'd13:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00011111_11111111;

    6'd14:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_00111111_11111111;

    6'd15:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_01111111_11111111;

    6'd16:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000000_11111111_11111111;

    6'd17:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000001_11111111_11111111;

    6'd18:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000011_11111111_11111111;

    6'd19:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00000111_11111111_11111111;

    6'd20:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00001111_11111111_11111111;

    6'd21:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00011111_11111111_11111111;

    6'd22:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_00111111_11111111_11111111;

    6'd23:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_01111111_11111111_11111111;

    6'd24:therm_data<=63'b0000000_00000000_00000000_00000000_0000000_11111111_11111111_11111111;

    6'd25:therm_data<=63'b0000000_00000000_00000000_00000000_0000001_11111111_11111111_11111111;

    6'd26:therm_data<=63'b0000000_00000000_00000000_00000000_0000011_11111111_11111111_11111111;

    6'd27:therm_data<=63'b0000000_00000000_00000000_00000000_0000111_11111111_11111111_11111111;

    6'd28:therm_data<=63'b0000000_00000000_00000000_00000000_0001111_11111111_11111111_11111111;

    6'd29:therm_data<=63'b0000000_00000000_00000000_00000000_0011111_11111111_11111111_11111111;

    6'd30:therm_data<=63'b0000000_00000000_00000000_00000000_0111111_11111111_11111111_11111111;

    6'd31:therm_data<=63'b0000000_00000000_00000000_00000000_1111111_11111111_11111111_11111111;

    6'd32:therm_data<=63'b0000000_00000000_00000000_00000001_1111111_11111111_11111111_11111111;

    6'd33:therm_data<=63'b0000000_00000000_00000000_00000001_1111111_11111111_11111111_11111111;

    6'd34:therm_data<=63'b0000000_00000000_00000000_00000011_1111111_11111111_11111111_11111111;

    6'd35:therm_data<=63'b0000000_00000000_00000000_00000111_1111111_11111111_11111111_11111111;

    6'd36:therm_data<=63'b0000000_00000000_00000000_00001111_1111111_11111111_11111111_11111111;

    6'd37:therm_data<=63'b0000000_00000000_00000000_00011111_1111111_11111111_11111111_11111111;

    6'd38:therm_data<=63'b0000000_00000000_00000000_00111111_1111111_11111111_11111111_11111111;

    6'd39:therm_data<=63'b0000000_00000000_00000000_01111111_1111111_11111111_11111111_11111111;

    6'd40:therm_data<=63'b0000000_00000000_00000000_11111111_1111111_11111111_11111111_11111111;

    6'd41:therm_data<=63'b0000000_00000000_00000001_11111111_1111111_11111111_11111111_11111111;

    6'd42:therm_data<=63'b0000000_00000000_00000011_11111111_1111111_11111111_11111111_11111111;

    6'd43:therm_data<=63'b0000000_00000000_00000111_11111111_1111111_11111111_11111111_11111111;

    6'd44:therm_data<=63'b0000000_00000000_00001111_11111111_1111111_11111111_11111111_11111111;

    6'd45:therm_data<=63'b0000000_00000000_00011111_11111111_1111111_11111111_11111111_11111111;

    6'd46:therm_data<=63'b0000000_00000000_00111111_11111111_1111111_11111111_11111111_11111111;

    6'd47:therm_data<=63'b0000000_00000000_01111111_11111111_1111111_11111111_11111111_11111111;

    6'd48:therm_data<=63'b0000000_00000000_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd49:therm_data<=63'b0000000_00000001_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd50:therm_data<=63'b0000000_00000011_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd51:therm_data<=63'b0000000_00000111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd52:therm_data<=63'b0000000_00001111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd53:therm_data<=63'b0000000_00011111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd54:therm_data<=63'b0000000_00111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd55:therm_data<=63'b0000000_01111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd56:therm_data<=63'b0000000_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd57:therm_data<=63'b0000001_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd58:therm_data<=63'b0000011_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd59:therm_data<=63'b0000111_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd60:therm_data<=63'b0001111_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd61:therm_data<=63'b0011111_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd62:therm_data<=63'b0111111_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    6'd63:therm_data<=63'b1111111_11111111_11111111_11111111_1111111_11111111_11111111_11111111;

    endcase

end

endmodule

上述代码转换为verilog-a后如下：

二进制转温度计码 译码器 VERILOG-A代码

`include "constants.vams"

`include "disciplines.vams"

module DECODER( VDD, GND, CLK, RST_N, INDATA, BIN_DATA, THERM_DATA);

input VDD, GND, CLK ,RST_N ;

electrical VDD, GND, CLK ,RST_N;

input [7:0] INDATA ;

electrical  [7:0] INDATA ;

output [1:0] BIN_DATA ;

electrical [1:0] BIN_DATA ;

output  [62:0] THERM_DATA ;

electrical [62:0] THERM_DATA ;

integer count = 0;

integer clock = 0;

integer flag_clk = 0;

integer indata [7:0];

integer bin_in_data [1:0];

integer th_in_data [5:0];

integer th_out_data  [62:0];

integer sum;

parameter real td = 0.1n;  

parameter real tr = 0.1n;  

parameter real tf = 0.1n;

parameter real vth_h = 0.9; // threshold voltage at inputs

parameter real vth_l = 0.3; // threshold voltage at inputs

genvar i ;

//clock

analog begin

        @(initial_step) begin

            count = 0 ;

            clock = 0 ;

            flag_clk = 0 ;

        end

        @( cross( V(CLK,GND)- V(VDD,GND), +1 ) ) begin  

            clock = 1 ;

            count = count + 1 ;

            if(count >= 100 ) count = 0 ;

        end

        @( cross( clock - 1 , +1) )  begin

            if(clock != 0) clock = 0 ;

            flag_clk = 1 ;  

        end

        if (V(RST_N)<vth_l) begin

            count = 0 ;

            clock = 0 ;

            flag_clk = 0 ;

        end

       

    end

   

// simple

    analog begin

        @( cross( flag_clk - 1 , +1) )  begin

            flag_clk = 0 ;

            for(i=0; i<8; i=i+1) begin

                if (V(INDATA[i]) > vth_h) indata[i] = 1;

                else indata[i] = 0;

            end

        end

        if (V(RST_N)< vth_l) begin

            indata[7] = 0 ;

            indata[6] = 0 ;

            indata[5] = 0 ;

            indata[4] = 0 ;

            indata[3] = 0 ;

            indata[2] = 0 ;

            indata[1] = 0 ;

            indata[0] = 0 ;

        end

       

        th_in_data[5] = indata[7];

        th_in_data[4] = indata[6];

        th_in_data[3] = indata[5];

        th_in_data[2] = indata[4];

        th_in_data[1] = indata[3];

        th_in_data[0] = indata[2];

        bin_in_data[1] = indata[1];

        bin_in_data[0] = indata[0];

    end

//                __                     __      

//               /\ \__                 /\ \__  

//   ___   __  __\ \ ,_\  _____   __  __\ \ ,_\  

//  / __`\/\ \/\ \\ \ \/ /\ '__`\/\ \/\ \\ \ \/  

// /\ \L\ \ \ \_\ \\ \ \_\ \ \L\ \ \ \_\ \\ \ \_

// \ \____/\ \____/ \ \__\\ \ ,__/\ \____/ \ \__\

//  \/___/  \/___/   \/__/ \ \ \/  \/___/   \/__/

//                          \ \_\                

//                           \/_/                

// Signal-Output

analog begin

    sum = 0;

    generate i (0,5)

        sum=sum+th_in_data[i]*pow(2,i);  

   

    for (i=0; i<63; i=i+1) begin

        if(i<sum)

            th_out_data[i]=1;

        else

            th_out_data[i]=0;

    end

    generate i (62,0)

        V(THERM_DATA[i])<+transition((V(VDD,GND)*th_out_data[i]),td,tr,tf);

   

    generate i (1,0)

        V(BIN_DATA[i])<+transition((V(VDD,GND)*bin_in_data[i]),td,tr,tf);

end

endmodule

演示结果可以移步投稿的视频观看，有问题可以在视频下方留言